1. Field of the Invention
The present invention relates generally to multi-core processor systems and more particularly to multi-core processor systems for avionics systems.
2. Description of the Related Art
In modern avionics systems (for example, in Integrated Modular Avionics (IMA) systems), partitioning operating systems are typically used to meet stringent safety- and mission-critical requirements. Aeronautical Radio Inc. (ARINC) has promulgated the “ARINC Specification 653: Avionics Application Standard Software Interface” family of specifications (generally referred to here as “ARINC 653”).
ARINC 653 defines an APplication EXecutive (APEX) for space and time partitioning for enabling multiple partitions to share a single processor and memory in order to guarantee that applications executing within one partition cannot adversely affect other partitions. Each partition in such an ARINC 653 system represents a separate application and makes use of memory space that is dedicated to it. Similarly, the APEX allots a dedicated time slice to each partition, thus creating time partitioning. Each ARINC 653 partition also supports multitasking within it.
ARINC 653 was defined assuming the use of a single core processor. However, the processor industry has transitioned to multi-core processors for various reasons. As a result, most high-end processors are multi-core processors.
However, the cores and master controllers of a multi-core processor often share hardware resources and can significantly interfere with each other's performance. This interference can violate the guarantee of robust partitioning (a guarantee that partitions do not interfere with each other) that is fundamental to ARINC 653 and IMA systems. As a result, when such multi-core processors are used to implement ARINC 653 systems, all but one of the cores in the multi-core processors is typically disabled. This is a significantly inefficient use of hardware, and the inefficiency worsens as the number of cores per processor increases.
There has been a partial response to this problem U.S. Pat. Publcn. No. 20100199280, issued to S. C. Vestal, et al. entitled, “SAFE PARTITION SCHEDULING ON MULTI-CORE PROCESSORS,” discloses an embodiment directed to a method of generating a set of schedules for use by a partitioning kernel to execute a plurality of partitions on a plurality of processor cores included in a multi-core processor unit. The method includes determining a duration to execute each of the plurality of partitions without interference and generating a candidate set of schedules using the respective duration for each of the plurality of partitions. The method further includes estimating how much interference occurs for each partition when the partitions are executed on the multi-core processor unit using the candidate set of schedules and generating a final set of schedules by, for at least one of the partitions, scaling the respective duration in order to account for the interference for that partition. The method further includes configuring the multi-core processor unit to use the final set of schedules to control the execution of the partitions using at least two of the cores. The necessity to support hosted functions with differing design assurance levels (DAL) that require the scheduling of partitions maintains disjoint DAL levels. This is an artificial constraint that generally generates undesired dead times. This also results in the necessity to synchronize the cores in the core processors making the design approach relatively complex. This constraint, as well as other constraints that exist, mean that the multicore processor will be less efficiently utilized. There is a need to obviate these deficiencies.
During multicore operation a concern is that a core may make excessive use of DDR memory access relative to the normal behavior. The result is that the processor capacity is significantly degraded for the other cores.